As the operating frequency of an LSI is increased, power-supply noise inside the LSI is increased. In order to reduce the power-supply noise, a capacitor element called on-chip capacitor or decoupling capacitor is formed on a power-supply line of the LSI. PTL 1 discloses a technique concerning the layout of such capacitor elements.
The technique disclosed in PTL 1 is a technique in which a target area in which a decoupling capacitance is formed is divided into a plurality of areas, and unit cells of the decoupling capacitance are arranged in each area. At this time, the unit cells are laid out such that the power consumption in each area does not exceed an average value that has previously been calculated.